1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to memory modules and methods of making same.
2. Description of Related Art
As densities of semiconductor memories increase, two-dimensional structures are no longer able to meet specified requirements. Accordingly, three-dimensional memories are becoming known, although manufacturing processes for fabricating three-dimensional memories pose special problems. One approach to creating memory structures in three dimensions involves forming memory components comprising conducting planes or surfaces disposed in horizontal layers of staircase structures.
The staircase structures may be formed by first laying down alternating layers of insulating material (e.g., oxide) and conducting material (e.g., polysilicon). Sequential mask/photo/etch steps can then be performed with photoresist being incrementally peeled back between etch steps, thereby performing etches of monotonically increasing depth to create multiple conducting surfaces of staircase structures.
A prior art staircase structure that supports a four-layer 3D memory device is illustrated in FIG. 1. The structure comprises a substrate 10 with conducting layers 15 and insulating layers 20 disposed alternately on the substrate 10. The structure has been subjected to multiple etches to form steps or areas 25 that expose surfaces of the conducting layers 15. Conducting elements 30 may connect the conducting layers 15 to higher layers (not shown) in the memory device.
A staircase structure such as that illustrated may be filled-in with insulating material, e.g., oxide (not shown in FIG. 1), and openings may be formed in the oxide to enable contact with the steps of the staircase. The contact openings may be filled with conducting material to create vertically-oriented conducting elements 30, thereby providing electrical access to surfaces of the conducting layers.
Staircase contact structures and other prior art structural elements and methods of manufacture for 3D memory devices must cope with significant challenges such as controlling simultaneous multi-step procedures required for etching as well as forming contact openings with extremely high aspect ratios that must land on very small steps and/or conducting layers.
The aforementioned problems need to be addressed and must be overcome in the face of ever-increasing die density.
A need thus exists for NAND based non-volatile memory, for example, three-dimensional (3D) semiconductor memory, contact structures that do not require widely varying and/or extremely large aspect ratios. A further need exists for a method of forming such 3D semiconductor memory contact structures.